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PRELIMINARY
SigmaTel, Inc.
Integrating Mixed-Signal Solutions
STAC9708/11
Multi-Channel AC'97 Codec With Multi-Codec Option
GENERAL DESCRIPTION:
SigmaTel's STAC9708/11 is a general purpose 18-bit, full duplex, audio codec that conforms to the analog component specification of AC'97 (Audio Codec 97 Component Specification Rev. 2.1). The STAC9708/11 incorporates SigmaTel's proprietary Sigma-Delta technology to achieve a DAC SNR in excess of 95dB. The DACs, ADCs, and mixer are integrated with analog I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. Also included are two additional high quality DACs, with independent volume control, for multi-channel applications. With SigmaTel's 3D stereo enhancement (SS3D), independently selectable on both LINE OUT and DAC OUT, the multi-channel mode immerses the user in a richer and livelier listening experience. The STAC9708/11 may be used as a secondary codec, with the STAC9704/07 as the primary, in a multiple codec configuration conforming to the AC'97 Rev. 2.1 specification. This configuration can provide true six-channel, AC-3 playback required for DVD applications. The STAC9708/11 communicates via the five-wire AC-Link to any digital component of AC'97 providing flexibility in the audio system design. Packaged in an AC'97 compliant 48-pin TQFP, the STAC9708/11 can be placed on the motherboard, daughter boards, add-on cards or PCMCIA cards.
FEATURES:
* * * * * * High performance technology Two additional high quality DAC's for multi-channel applications 18-bit full duplex stereo ADC, DACs AC-Link protocol compliance Multiple power supply options Pin compatible with the STAC9704/07 * * * * * * SigmaTel Surround Enhancement (SS3D) Stereo
Energy saving power down modes Multi-Codec option (Intel AC'97 rev 2.1) Six analog line-level inputs 48-pin TQFP SNR > 95 dB through Mixer and DAC
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ORDERING INFORMATION:
PART NUMBER
STAC9708T STAC9711T
PACKAGE
48-pin TQFP 7mm x7mm x 1.4mm 48-pin TQFP 7mmx7mm x 1.4mm
TEMPERATURE RANGE
0o C to +70o C 0o C to +70o C
SUPPLY RANGE
DVdd = 3.3V or 5V, AVdd = 5V DVdd = 3.3V, AVdd = 3.3V
SigmaTel reserves the right to change specifications without notice.
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Table of Contents
General Description Ordering Information 1. PIN/SIGNAL Descriptions 1.1 Digital I/O 1.2 Analog I/O 1.3 Filter/References/GPIO 1.4 Power and Ground Signal 2. AC-Link 2.1 Clocking 2.2 Reset 3. Digital Interface 3.1 AC-Link Digital Serial Interface Protocol 3.1.1 AC-Link Audio Output Frame (SDATA_OUT)
Preliminary
STAC9708/11
3.1.2.2 Slot 2: Status Data Port 3.1.2.3 Slot 3: PCM Record Left Channel 3.1.2.4 Slot 4: PCM Record Right Channel 3.1.2.5 Slots 5-12: Reserved 21 21 21 21 21 22 23 25 25 25 26 27 27 27 28 28 30 30 30 31 32 33 33 33 33 33 34 36 36 36 36 36 37
1 2 9 9 10 11 12 12 13 13 14 14
3.2 AC-Link Low Power Mode 3.2.1 Waking up the AC-Link 4. STAC9708/11 Mixer 4.1 Mixer Input. 4.2 Mixer Output 4.3 PC Beep Implementations 4.4 Programming Registers 4.4.1 Reset Register 4.4.2 Play Master Volume Registers 4.4.3 PC Beep Register 4.4.4 Analog Mixer Input Gain 4.4.5 Record Select Control 4.4.6 Record Gain Registers 4.4.7 General Purpose Register 4.4.8 3D Control Register 4.4.9 Multi-Channel Programming 4.4.10 Powerdown Control/Status 4.4.10.1 External Amplifier Power Down (EAPD) Control 4.4.11 Extended Audio ID Register 4.4.12 Extended Audio Status Register 4.4.13 Analog Special Register 4.4.14 Vendor ID1 and ID2 Registers 5. Low Power Modes 6. Multiple Codec Support 6.1 Primary/Secondary Codec Selection 6.1.1 Primary Codec Operation 6.1.2 Secondary Codec Operation 6.2 Secondary Codec Register Access Definitions 7. Testability
15 16 17 17 17 17 17 18 18 18 18 18 19
3.1.1.1 Slot 1: Command Address Port 3.1.1.2 Slot 2: Command Data Port 3.1.1.3 Slot 3: PCM Playback Left Channel 3.1.1.4 Slot 4: PCM Playback Right Channel 3.1.1.5 Slot 5: Reserved 3.1.1.6 Slot 6: PCM Center Channel 3.1.1.7 Slot 7: PCM Left Surround Channel 3.1.1.8 Slot 8: PCM Right Surround Channel 3.1.1.9 Slot 9: PCM Low Frequency Channel 3.1.1.10 Slot 10: PCM Alternate Left 3.1.1.11 Slot 11: PCM Alternate Right 3.1.1.12 Slot 12: Reserved 3.1.2 AC-Link Audio Input Frame (SDATA_In) 3.1.2.1 Slot 1: Status Address Port
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8. Extended Codec Functionality 8.1 Anti-Pop Circuitry 9. AC Timing Characteristics 9.1 Cold Reset. 9.2 Warm Reset 9.3 Clocks 9.4 Data Setup and Hold 9.5 Signal Rise and Fall Times 9.6 AC-Link Low Power Mode Timing 9.7 ATE Test Mode 10. Electrical Specifications 10.1 Absolute Maximum Conditions 10.2 Recommended Operating Conditions 10.3 Power Consumption 10.4 AC-Link Static Digital Specifications 10.5 9708 Analog Performance Characteristics 10.6 9711 Analog Performance Characteristics APPENDIX A APPENDIX B
Preliminary
38 38 38 38 39 40 41 42 43 44 45 45 45 46 46 47 49 51 52
STAC9708/11
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Table of Contents - Tables
Table 1 - Package Dimensions Table 2 - Pin Designation Table 3 - Digital Signal List Table 4 - Analog Signal List
Preliminary
6 6 9 10 11 11 24 25 26 27 27 28 29 29 30 31 31 32 36 37 36 36 37 38 39 40 40
5
STAC9708/11
44 45 45 46 48
Table 30 - Operating Conditions Table 28 - Power Consumption Table 29 - AC-Link Static Specifications Table 30 - 9708 Analog Performance Characteristics Table 31 - 9711 Analog Performance Characteristics
Table 5 - Filtering and Voltage References Table 6 - 9708/11 Power Signal List Table 7 -Mixer Functional Connections Table 8 - Programming Registers Table 9 - Play Master Volume Register Table 10 - PC Beep Register Table 11 - Analog Mixer Input Gain Register Table 12, 13 - Record Select Control Registers Table 14 - Record Gain Registers Table 15 - General Purpose Registers Table 16, 17 - 3D Control Registers Table 18- Multi-Channel Programming Register Table 19 - Powerdown Status Registers Table 20 - Low Power Modes Table 21 - Codec ID Selection Table 22 - Secondary Codec Register Access Slot 0 Bit Definitions Table 23 - Cold Reset Table 24 - Warm Reset Table 25 - Clocks Table 26 - Data Setup and Hold Table 27 - Signal Rise and Fall Times Table 28 - AC-Link Low Power Mode Timing Table 29 - ATE Test Mode
Table of Contents - Figures
Figure 1 - Package Outline Figure 2 - STAC9708 Block Diagram Figure 3 - Connection Diagram Figure 4 - STAC9708 AC-Link Figure 5 - AC'97 Standard Bi-directional Figure 6 - AC-Link Audio Output Frame Figure 7 - Start of an Audio Output Frame Figure 8 - STAC9708 Audio Input Frame Figure 9 - Start of an Audio Input Frame Figure 10 - STAC9708 Powerdown Timing Figure 11 - STAC9708 Mixer Functional Diagram Figure 12 - Example of STAC9708 Powerdown/ Powerup flow Figure 13 - STAC9708 Powerdown/Powerup with analog still alive Figure 14 - Cold Reset Figure 15 - Warm Reset Figure 16 - Clocks Figure 17 - Data Setup and Hold Figure 18 - Signal Rise and Fall Times Figure 19 - AC-Link Low Power Mode Timing Figure 20 - ATE Test Mode 6 7 8 12 15 15 16 19 20 22 23 35 35 38 39 39 40 41 42 42
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Figure 1. Package Outline
D D1
26 38
Preliminary
KEY
a
STAC9708/11
Table 1. Package Dimensions 9708/11 DIMENSION TQFP 9.00 mm 7.00 mm 9.00 mm 7.00 mm 0.20 mm 0.50 mm 1.4 mm
SigmaTel
E E1
e
STAC9708/11 48 pin TQFP
14 2
D D1 E E1 a (lead width) e (pitch) thickness
Table 2. Pin Designation
PIN # 1 2 3 4 5 6 7 8 9 10 11 12
SIGNAL NAME DVdd1 XTL_IN XTL_OUT DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 SYNC RESET# PC_BEEP
PI N# 13 14 15 16 17 18 19 20 21 22 23 24
SIGNAL NAME PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R
PIN # 25 26 27 28 29 30 31 32 33 34 35 36
SIGNAL NAME AVdd1 AVss1 Vref Vrefout AFILT1 AFILT2 CAP1 CAP2 CAP3 APOP LINE_OUT_L LINE_OUT_R
PIN # 37 38 39 40 41 42 43 44 45 46 47 48
SIGNAL NAME MONO_OUT AVdd2 DAC_OUT_L NC DAC_OUT_R AVss2 NC NC CID0 CID1 EAPD NC
# denotes active low
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Preliminary
Figure 2. STAC9708 Block Diagram
2 mono sources 4 stereo sources Power Management
PCM out DACs 48Kss
Digital
STAC9708/11
mono stereo
DAC_OUT M IXER
Analog mixing and Gain control
Mic Boost 0/20 dB M U X
DAC DAC DAC
AC-link
SYNC BIT_CLK SDATA_OUT SDATA_IN RESET
Interface
LINE_OUT MONO_OUT M IC 1 M IC 2
Registers 64 x 16 bits
DAC
PCM in ADCs
ADC ADC
48Kss
Multi-Codec
ID0 ID1
The STAC9708/11 block diagram, above, illustrates its primary functional blocks. It performs fixed 48K sample rate D-A & A-D conversion, mixing, and analog processing. The digital interface communicates with the AC'97 controller via the five wire AC-Link and contains the 64 word by 16-bit registers. Four, fixed 48Ks/s DAC's support two stereo PCM-out channels for surround sound applications requiring four speakers. The digital mix of all software sources, including the internal synthesizer and any other digital sources, is performed in the digital controller. The Mixer block mixes the PCM_OUT with any analog sources, then outputs to LINE_OUT. The surround DACs are output to DAC_OUT, and this stereo output has independent volume control. In addition, the surround DACs can be input to the Mixer block and output to LINE_OUT. The MONO_OUT delivers either mic only or a mono mix of sources from the mixer. The two fixed 48Ks/s ADC's take any mix of mono or stereo sources and convert it to a stereo PCM-in signal. All ADC's and DAC's operate at 18-bit resolution. The STAC9708/11 is designed primarily to support multi-channel, 4-speaker PC audio. However, true AC-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-codec option in the STAC9708/11. Using this option with a STAC9704/07 as the primary codec, and the STAC9708 as the secondary codec, 6-channel output can be achieved in an AC'97 architecture. Also, the STAC9708/11 provides for a stereo enhancement feature, Sigmatel Surround 3D or SS3D. SS3D provides the listener with several options to expand the soundstage beyond the normal 2-speaker arrangement. Together with the logic component (controller or advanced core logic chip-set) of AC'97, STAC9708/11 can be SoundBlaster(R) and Windows Sound System(R) compatible. SoundBlaster(R) is a registered trademark of Creative Labs. Windows(R) is a registered trademark of Microsoft Corporation.
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Preliminary
STAC9708/11
Figure 3. Connection Diagram - See Appendix A for an alternative connection diagram when using separate supplies. See Appendix B for specific connection requirements prior to operation.
2 ohm * Ferrite Bead *
* Suggested
3.3V or 5V 5%
0.1uF 0.1uF 1uF 0.1uF 38 AVdd2 1 DVdd1
10uF
0.1uF
25 AVdd1 12
9 DVdd2 XTL_IN 2 33pF
P C _ B EE P XTL_OUT PHONE 3
24.576MHz
13
33pF SDATA_OUT 5 6 BIT_CLK 8
14 AUX_L 15 AUX_R 16 VIDEO_L
SDATA_IN
SigmaTel
VIDEO_R
10 SYNC 11 RESET 45 CID0 46 CID1
17
STAC9708/11
18 CD_L
19
CD_GND 20 CD_R 21 MIC1 22 MIC2 23 CAP1 Vrefout 32 CAP2 31 33 27 Vref 0.1uF 28 10uF
10uF
0.1uF
LINE_IN_L
CAP3 24
10uF 22uF
LINE_IN_R
45 APOP 34 47 35 LINE_OUT_L LINE_OUT_R AFILT1 37 MONO_OUT 30 AFILT2 36
CID0
46 EAPD
CID1
560 - 1000pF 29 560 - 1000pF
AVss1
26
AVss2 42
DVss1 4
DVss2 7
DAC_OUT_L 39
DAC_OUT_R 41
** Teminate ground plane as close to power supply as possible
NOTE: Pins 31, 33, 34, 40
43, 44, and 48 are No Connects Brd Analog Gnd Brd Digital Gnd
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Preliminary
STAC9708/11
1. PIN/SIGNAL DESCRIPTIONS 1.1 Digital I/O
These signals connect the STAC9708/11 to its AC'97 controller counterpart, an external crystal, multicodec selection and external audio amplifier. Table 3. Digital Signal List
SIGNAL NAME RESET # XTL_IN XTL_OUT SYNC BIT_CLK SDATA_OUT SDATA__IN CID0 CID1 EAPD # denotes active low
TYPE I I O I O I O I I O
DESCRIPTION AC'97 Master H/W Reset 24.576 MHz Crystal 24.576 MHz Crystal 48 kHz fixed rate sample sync 12.288 MHz serial data clock Serial, time division multiplexed, AC'97 input stream Serial, time division multiplexed, AC'97 output stream Multi-Codec ID select - bit 0 Multi-Codec ID select - bit 1 External Amplifier Power Down
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1.2 Analog I/O
Preliminary
STAC9708/11
These signals connect the STAC9708/11 to analog sources and sinks, including microphones and speakers. Table 4. Analog Signal List
SIGNAL NAME PC-BEEP PHONE MIC1 MIC2 LINE-IN-L LINE-IN-R CD-L CD-GND CD-R VIDEO-L VIDEO-R AUX-L AUX-R LINE-OUT-L LINE-OUT-R MONO-OUT
TYPE I I I I I I I I I I I I I O O O
DESCRIPTION PC Speaker beep pass-through From telephony subsystem speakerphone (or DLP - Down Line Phone) Desktop Microphone Input Second Microphone Input Line In Left Channel Line In Right Channel CD Audio Left Channel CD Audio analog ground CD Audio Right Channel Video Audio Left Channel Video Audio Right Channel Aux Left Channel Aux Right Channel Line Out Left Channel Line Out Right Channel To telephony subsystem speakerphone (or DLP - Down Line Phone)
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DAC_OUT_L DAC_OUT_R O O
Preliminary
STAC9708/11
Surround DAC Out Left Channel Surround DAC Out Right Channel
* Note: any unused input pins should have a capacitor (1 uF suggested) to ground.
1.3 Filter/References/GPIO
These signals are connected to resistors, capacitors, specific voltages, or provide general purpose I/O. Table 5. Filtering and Voltage References
SIGNAL NAME Vref Vrefout AFILT1 AFILT2 CAP1 CAP2 CAP3 APOP EAPD
TYPE O O O O O O O O O
DESCRIPTION Reference Voltage Reference Voltage out 5mA drive (intended for mic bias) Anti-Aliasing Filter Cap - ADC channel Anti-Aliasing Filter Cap - ADC channel Analog Output Hold-Off Delay ADC reference Cap Anti-Pop Power Sustain Delay Anti-Pop Output Ground Shunt Control External Amplifier Power Down Control
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1.4 Power and Ground Signals
Preliminary
STAC9708/11
Table 6. Power Signal List STAC9708/11 SIGNAL NAME AVdd1 AVdd2 AVss1 AVss2 DVdd1 DVdd2 DVss1 DVss2 TYPE I I I I I I I I STAC9708 Analog Vdd = 5.0V Analog Vdd = 5.0V Analog Gnd Analog Gnd Digital Vdd = 5.0V or 3.3V Digital Vdd = 5.0V or 3.3V Digital Gnd Digital Gnd STAC9711 Analog Vdd = 3.3V Analog Vdd = 3.3V Analog Gnd Analog Gnd Digital Vdd = 3.3V Digital Vdd = 3.3V Digital Gnd Digital Gnd
2. AC-LINK
Below is the figure of the AC-Link point to point serial interconnect between the STAC9708/11 and its companion controller. All digital audio streams and command/status information are communicated over this AC-Link. Please refer to the "Digital Interface" section 3 for details.
Figure 4. STAC9708/11's AC-Link to its companion controller
SYNC
XTAL_IN
Digital DC'97 Controller
BIT_CLK
SDATA_OUT SDATA_IN
XTAL_OUT
STAC9708/11
RESET
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2.1 Clocking
Preliminary
STAC9708/11
STAC9708/11 derives its clock internally from an externally connected 24.576 MHz crystal or an oscillator through the XTAL_IN pin. Synchronization with the AC'97 controller is achieved through the BIT_CLK pin at 12.288 MHz (half of crystal frequency). The beginning of all audio sample packets, or "Audio Frames", transferred over AC-Link is synchronized to the rising edge of the "SYNC" signal driven by the AC'97 controller. Data is transitioned on AC-Link on every rising edge of BIT_CLK, and subsequently sampled by the receiving side on each immediately following falling edge of BIT_CLK.
2.2 Reset
There are 3 types of resets as detailed under "Timing Characteristics".
1. 2. 3.
a "cold" reset where all STAC9708/11 logic and registers are initialized to their default state a "warm" reset where the contents of the STAC9708/11 register set are left unaltered a "register" reset which only initializes the STAC9708/11 registers to their default states
After signaling a reset to the STAC9708/11, the AC'97 controller should not attempt to play or capture audio data until it has sampled a "Codec Ready" indication via register 26h from the STAC9708/11. For proper reset operation SDATA_OUT should be "0" during "cold" reset.
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3. DIGITAL INTERFACE
Preliminary
STAC9708/11
3.1 AC-Link Digital Serial Interface Protocol
The STAC9708/11 communicates to the AC'97 controller via a 5-pin digital serial AC-Link interface, which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, commands and status information are communicated over this point-to-point serial interconnect. The AC-Link handles multiple inputs, and output audio streams, as well as control register accesses using a time division multiplexed (TDM) scheme. The AC'97 controller synchronizes all AC-Link data transaction. The following data streams are available on the STAC9708/11: * * * * PCM Playback PCM Record data Control Status 4 output slots 2 input slots 2 output slots 2 input slots 4 Channel composite PCM output stream 2 Channel composite PCM input stream Control register write port Control register read port
Synchronization of all AC-Link data transactions is handled by the AC'97 controller. The STAC9708/11 drives the serial bit clock onto AC-Link. The AC'97 controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver of ACLink data, STAC9708/11 for outgoing data and AC'97 controller for incoming data, samples each serial bit on the falling edges of BIT_CLK. The AC-Link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit positions) time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A "1" in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is "tagged" invalid, it is the responsibility of the source of the data, (STAC9708/11 for the input stream, AC'97 controller for the output stream), to stuff all bit positions with 0's during that slot's active time. SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the "Tag Phase". The remainder of the audio frame where SYNC is low is defined as the "Data Phase". Additionally, for power savings, all clock, sync, and data signals can be halted.
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Preliminary
STAC9708/11
SYNC OUTGOING STREAMS INCOMING STREAMS TAG PHASE
TAG CMD ADR STATUS ADR CMD DATA PCM LEFT PCM RT NA PCM CTR PCM LSURR PCM RSURR PCM LFE PCM LALT PCM RALT RSVD
STATUS DATA
TAG
PCM LEFT
PCM RT
NA
NA
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
DATA PHASE
Figure 5. AC'97 Standard Bi-directional Audio Frame
3.1.1 AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the STAC9708/11 DAC inputs, and control registers. Each audio output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure. Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio frame. If the "Valid Frame" bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12 bit positions sampled by the STAC9708/11 indicate which of the corresponding 12 times slots contain valid data. In this way data streams of differing sample rates can be transmitted across AC-Link at its fixed 48kHz audio frame rate. The following diagram illustrates the time slot based AC-Link protocol. Figure 6. AC-Link Audio Output Frame
Data Phase Tag Phase 20.8 uS (48 kHZ)
SYNC BIT_CLK
12.288 MHz
SDATA_OUT
valid Frame
slot1
slot2
slot(12) "0"
CID1 CID0
19
"0"
19
"0"
19
"0"
19
"0"
End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the STAC9708/11 samples the assertion of SYNC. This following edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC'97 controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the STAC9708/11 on
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Preliminary
STAC9708/11
the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
Figure 7. Start of an Audio Output Frame
STAC9708 samples SYNC assertion here
SYNC
STAC9708 samples first SDATA_OUT bit of frame here
BIT_CLK
valid Frame
SDATA_OUT
slot1
slot2
End of previous audio frame
SDATA_OUT's composite stream is MSB justified (MSB first) with all non-valid slots' bit positions stuffed with 0's by the AC'97 controller. When mono audio sample streams are sent from the AC'97 controller, it is necessary that BOTH left and right sample stream time slots be filled with the same data.
3.1.1.1 Slot 1: Command Address Port
The command port is used to control features, and monitor status (see Audio Input Frame Slots 1 and 2) of the STAC9708/11 functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification). The control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Audio output frame slot 1 communicates control register address, and write/read command information to the STAC9708/11. Command Address Port bit assignments: Bit (19) Read/Write command (1= read, 0=write) Bit (18:12) Control Register Index (64 16-bit locations, addressed on even byte boundaries) Bit (11:0) Reserved (Stuffed with 0's) The first bit (MSB) sampled by STAC9708/11 indicates whether the current control transaction is a read or a write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are reserved and must he stuffed with 0's by the AC'97 controller.
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STAC9708/11
3.1.1.2 Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (as indicated by Slot 1, bit 19) Bit (19:4) Bit (3 :0) Control Register Write Data (Stuffed with 0's if current operation is a read) Reserved (Stuffed with 0's)
If the current command port operation is a read then the entire slot time must be stuffed with 0's by the AC'97 controller.
3.1.1.3 Slot 3: PCM Playback Left Channel
Audio output frame slot 3 is the composite digital audio left playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's.
3.1.1.4 Slot 4: PCM Playback Right Channel
Audio output frame slot 4 is the composite digital audio right playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's.
3.1.1.5 Slot 5: Reserved
Audio output frame slot 5 is reserved for modem operation and is not used by the STAC9708/11.
3.1.1.6 Slot 6: PCM Center Channel
Audio output frame slot 6 is the composite digital audio center stream used in a multi-channel application where the STAC9708/11 is programmed to accept the primary DAC PCM data from slots 6 and 9. As a programming option, PCM data from slots 6 and 9 may be used to supply data to the surround DACs when slots 7 and 8 are used to drive the primary DACs. Please refer to the register programming section for details on the multi-channel programming options.
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Preliminary
STAC9708/11
3.1.1.7 Slot 7: PCM Left Surround Channel
Audio output frame slot 7 is the composite digital audio left surround stream. In the default state, the STAC9708/11 accepts PCM data from slots 7 and 8 for the surround DACs, for output to the DAC_OUT pins. As a programming option, PCM data from slots 7 and 8 may be used to supply data to the primary DACs when slots 6 and 9 are used to drive the surround DACs. Please refer to the register programming section for details on the multi-channel programming options.
3.1.1.8 Slot 8: PCM Right Surround Channel
Audio output frame slot 8 is the composite digital audio right surround stream. In the default state, the STAC9708/11 accepts PCM data from slots 7 and 8 for the surround DACs, for output to the DAC_OUT pins. As a programming option, PCM data from slots 7 and 8 may be used to supply data to the primary DACs when slots 6 and 9 are used to drive the surround DACs. Please refer to the register programming section for details on the multi-channel programming options.
3.1.1.9 Slot 9: PCM Low Frequency Channel
Audio output frame slot 9 is the composite digital audio low frequency stream used in a multichannel application where the STAC9708/11 is programmed to accept the primary DAC PCM data from slots 6 and 9. As a programming option, PCM data from slots 6 and 9 may be used to supply data to the surround DACs when slots 7 and 8 are used to drive the primary DACs. Please refer to the register programming section for details on the multi-channel programming options.
3.1.1.10 Slot 10: PCM Alternate Left
Audio output frame slot 10 is the composite digital audio alternate left stream used in a multichannel application where the STAC9708/11 is programmed to accept the primary DAC PCM data from slots 6 and 9. Please refer to the register programming section for details on the multi channel programming options.
3.1.1.11 Slot 11: PCM Alternate Right
Audio output frame slot 11 is the composite digital audio alternate right stream used in a multi-channel application where the STAC9708/11 is programmed to accept the primary DAC PCM data from slots 6 and 9. Please refer to the register programming section for details on the multi channel programming options.
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Preliminary
STAC9708/11
3.1.1.12 Slot 12: Reserved
Audio output frame slot 12 is reserved for modem operations and is not used by the STAC9708/11.
3.1.2 AC-Link Audio Input Frame (SDATA_IN)
The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC'97 controller. As is the case for audio output frame, each AC-Link audio input frame consists of 12, 20-bit time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure. Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the STAC9708/11 is in the "Codec Ready" state or not. If the "Codec Ready" bit is a 0, this indicates that STAC9708/11 is not ready for normal operation. This condition is normal following the de-assertion of power on reset, for example, while STAC9708/11's voltage references settle. When the AC-Link "Codec Ready" indicator bit is a 1, it indicates that the AC-Link and STAC9708/11 control/status registers are in a fully operational state. The AC'97 controller must further probe the Powerdown Control Status Register (refer to Mixer Register section) to determine exactly which subsections, if any, are ready. Prior to any attempts at putting STAC9708/11 into operation the AC'97 controller should poll the first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that STAC9708/11 has become "Codec Ready". Once the STAC9708/11 is sampled "Codec Ready", the next 12 bit positions sampled by the AC'97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. The following diagram illustrates the time slot based AC-Link protocol. Figure 8. STAC9708/11 Audio Input Frame
Data Phase Tag Phase 20.8 uS (48 kHZ)
SYNC BIT_CLK
12.288 MHz
SDATA_IN
valid Frame
slot1
slot2
slot(12) "0"
"0"
"0"
19
"0"
19
"0"
19
"0"
19
"0"
End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12
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STAC9708/11
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, STAC9708/11 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the STAC9708/11 transitions SDATA_IN into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. Figure 9. Start of an Audio Input Frame
STAC9708 samples SYNC assertion here
SYNC
STAC9708 samples first SDATA_OUT bit of frame here
BIT_CLK
Codec Ready
SDATA_IN
slot1
slot2
End of previous audio frame
SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0's by STAC9708/11. SDATA_IN data is sampled on the falling edges of BIT_CLK.
3.1.2.1 Slot 1: Status Address Port
The status port is used to monitor status for STAC9708/11 functions including, but not limited to, mixer settings, and power management. Audio input frame slot 1's stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged "valid" by STAC9708/11 during slot 0) Status Address Port hit assignments: Bit (19) RESERVED (Stuffed with 0) Bit (18;12) Control Register Index (Echo of register index for which data is being returned) Bit (11:0) RESERVED (Stuffed with 0's) The first bit (MSB) generated by STAC9708/11 is always stuffed with a 0. The following 7 bit positions communicate the associated control register address, and the trailing 12 bit positions are stuffed with 0's by STAC9708/11.
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Preliminary
STAC9708/11
3.1.2.2 Slot 2: Status Data Port
The status data port delivers 16-bit control register read data. Bit (19:4) Bit (3 :0) Control Register Read Data RESERVED (Stuffed with 0's if tagged "invalid") (Stuffed with 0's)
If Slot 2 is tagged "invalid" by STAC9708/11, then the entire slot will be stuffed with 0's.
3.1.2.3 Slot 3: PCM Record Left Channel
Audio input frame slot 3 is the left channel output of STAC9708/11 input MUX, post-ADC. STAC9708/11 ADCs are implemented to support 18-bit resolution. STAC9708/11 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot.
3.1.2.4 Slot 4: PCM Record Right Channel
Audio input frame slot 4 is the right channel output of STAC9708/11 input MUX, post-ADC. STAC9708/11 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot.
3.1.2.5 Slots 5-12: Reserved
Audio input frame slots 5-12 are not used by the STAC97908/11 and are always stuffed with 0's.
3.2 AC-Link Low Power Mode
The STAC9708/11 AC-Link can be placed in the low power mode by programming register 26h to the appropriate value. Both BIT_CLK and SDATA_IN will be brought to, and held at a logic low voltage level. The AC'97 controller can wake up the STAC9708/11 by providing the appropriate reset signals.
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Preliminary
Figure 10. STAC9708/11 Powerdown Timing
SYNC
STAC9708/11
BIT_CLK
slot2 per frame TAG Write to 0x20 Data PR4
SDATA_OUT
SDATA_IN
slot2 per frame
TAG
Note: BIT_CLK not to scale
BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time) following the decode of the write to the Powerdown Register (26h) with PR4. When the AC'97 controller driver is at the point where it is ready to program the AC-Link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame (all sources of audio input have been neutralized). The AC'97 controller should also drive SYNC, and SDATA_OUT low after programming the STAC9708/11 to this low power mode.
3.2.1 Waking up the AC-Link
Once the STAC9708/11 has halted BIT_CLK, there are only two ways to "wake up" the AC-Link. Both methods must be activated by the AC'97 controller. The AC-Link protocol provides for a "Cold AC'97 Reset", and a "Warm AC'97 Reset". The current power down state would ultimately dictate which form of reset is appropriate. Unless a "cold" or "register" reset (a write to the Reset register) is performed, wherein the AC'97 registers are initialized to their default values, registers are required to keep state during all power down modes. Once powered down, re-activation of the AC-Link via reassertion of the SYNC signal must not occur for a minimum of 4 audio frame times following the frame in which the power down was triggered. When AC-Link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15). Cold Reset - a cold reset is achieved by asserting RESET# for the minimum specified time. By driving RESET# low, BIT_CLK, and SDATA_IN will be activated, or re-activated as the case may be, and all STAC9708/11 control registers will be initialized to their default power on reset values. Note: RESET# is an asynchronous input. # denotes active low
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STAC9708/11
Warm Reset - a warm reset will re-activate the AC-Link without altering the current STAC9708/11 register values. A warm reset is signaled by driving SYNC high for a minimum of 1us in the absence of BIT_CLK. Note: Within normal audio frames, SYNC is a synchronous input. However, in the absence of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the STAC9708/11.
4. STAC9708/11 MIXER
The STAC9708/11 mixer is designed to the AC'97 specification to manage the playback and record of all digital and analog audio sources in the PC environment. These include: * * * * * * System Audio: digital PCM input and output for business, games and multimedia CD/DVD: analog CD/DVD-ROM Redbook audio with internal connections to Codec mixer Mono microphone: choice of desktop mic, with programmable boost and gain Speakerphone: use of system mic and speakers for telephone, DSVD, and video conferencing Video: TV tuner or video capture card with internal connections to Codec mixer AUX/synth: analog FM or wavetable synthesizer, or other internal source
Figure 11. STAC9708/11 Mixer Functional Diagram
PCM out Surround
3D D/A vol mute mute mute mute mute mute mute mute mute -6 dB
DAC Volume
DAC OUT
PCM out
D/A PC_BEEP Phone MIC1 MIC2 LINE IN CD Video AUX 20dB
vol vol vol vol vol vol vol vol
Analog Audio Sources
3D -6 dB M U
X
Master Volume Mono Volume
LINE OUT MONO OUT
KEY Mono Analog Stereo Analog Digital
M U X
Master Input Volume
A/D A/D
PCM IN
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Table 7. Mixer Functional Connections
STAC9708/11
SOURCE PC_Beep PHONE MIC1 MIC2 LINE_IN CD VIDEO AUX PCM out LINE_OUT DAC_OUT MONO_OUT PCM in
FUNCTION PC beep pass thru speakerphone or DLP in desktop microphone second microphone external audio source audio from CD-ROM audio from TV tuner or video camera upgrade synth or other external source digital audio output from AC'97 Controller stereo mix of all sources surround stereo DAC output mic or mix for speakerphone or DLP out digital audio input to AC'97 Controller
CONNECTION from PC beeper output from telephony subsystem from mic jack from second mic jack from line-in jack cable from CD-ROM cable from TV or VidCap card internal connector AC-Link To output jack To output jack to telephony subsystem AC-Link
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4.1 Mixer Input
Preliminary
STAC9708/11
The mixer provides recording and playback of any audio sources or output mix of all sources. The STAC9708/11 supports the following input sources: * * * any mono or stereo source mono or stereo mix of all sources 2-channel input w/mono output reference (mic + stereo mix)
Note: any unused input pins should have a capacitor (1 uF suggested) to ground.
4.2
Mixer Output
The mixer generates two distinct outputs: * a stereo mix of all sources for output to the LINE_OUT * a stereo mix of the surround DACs for output to the DAC_OUT * a mono, mic only or mix of all sources for MONO_OUT
* Note: Mono output of stereo mix is attenuated by -6 dB .
4.3 PC Beep Implementation
PC Beep is active on power up and defaults to an unmuted state. The user should mute this input before using any other mixer input because the PC Beep input can contribute noise to the lineout during normal operation.
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4.4 Programming Registers:
Preliminary
STAC9708/11
Table 8. Programming Registers
REG # 00h 02h 04h NAME Reset Master Volume D15 X Mute D14 SE4 X X X X X X X X X X X X X X X PR6 ID0 X X X X 0 1 D13 SE3 X X X X X X X X X X X X X 3D X PR5 X X X X X 0 1 D12 SE2 ML4 GL4 X X X X GL4 GL4 GL4 GL4 GL4 X X X X PR4 X D11 SE1 ML3 GL3 X X X X GL3 GL3 GL3 GL3 GL3 X GL3 X X PR3 X D10 SE0 ML2 GL2 X X X X GL2 GL2 GL2 GL2 GL2 SL2 GL2 X X PR2 X X ML2 X X 0 1 D9 ID9 ML1 GL1 X X X X GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX X PR1 X X ML1 X X 1 1 D8 ID8 ML0 GL0 X X X X GL0 GL0 GL0 GL0 GL0 SL0 GL0 MS X PR0 X X D7 ID7 X X X X X X X X X X X X X LPBK X X SDAC D6 ID6 X X X X X 20dB X X X X X X X X X X X X X X X 0 0 D5 ID5 X X X X X X X X X X X X X X X X X X X X X 0 0 D4 ID4 MR4 GR4 MM4 PV3 GN4 GN4 GR4 GR4 GR4 GR4 GR4 X X X X X X X MR4 X X 0 0 D3 ID3 MR3 GR3 MM3 PV2 GN3 GN3 GR3 GR3 GR3 GR3 GR3 X GR3 X D2 ID2 MR2 GR2 MM2 PV1 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 X D1 ID1 MR1 GR1 MM1 PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 X DP1 DAC X X MR1 DAC -6dB MC1 0 0 D0 ID0 MR0 GR0 MM0 X GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 X DP0 ADC X X MR0 ADC -6dB MC0 0 0 DE FAULT 6940h 8000h 8808h 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 000Fh 0000h 0000h 8080h 0000h 0000h 8384h 7608h
Surround DAC Mute Mixer Volume 06h Master Volume Mute Mono 0Ah PC_BEEP Volume Mute 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 26h 28h 2Ah 38h 6Ch 74h 7Ch 7Eh Phone volume Mic Volume Line In Volume CD Volume Video Volume AUX Volume Mute Mute Mute Mute Mute Mute
PCM Out Volume Mute Record Select Record Gain General Purpose 3D Control Powerdown Ctrl/Stat Extended Audio ID Extended Audio Status Control Surround DAC Master Volume Analog Special Multi-Channel Selection Vendor ID1 Vendor ID2 X Mute X X EAPD ID1 X Mute Left X X 1 0
DPR1 DPR0 REF X X MR3 X X 0 1 ANL X X MR2 X X 1 0
PWD X SDAC ML4 ML3 X X 0 1 X X 0 0
SDAC Ready ML0 Mute Right X X X 1 0 X 1 0
Notes: 1. All registers not shown and bits containing an X are reserved. 2. Any reserved bits, marked X, can be written to but are don't care upon read back. 3. PC_BEEP default to 0000h, mute off. 4. If optional bits D13, D5 of register 02h or D5 of register 06h are set to 1, then the corresponding attenuation is set to 46dB and the register reads will produce 1Fh as a value for this attenuation/gain block.
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Preliminary
STAC9708/11
4.4.1 Reset Register (Index 00h)
Writing any value to this register performs a register reset, which causes all registers to revert to their default values. Reading this register returns the ID code of the part.
4.4.2 Play Master Volume Registers (Index 02h, 38h, and 06h)
These registers manage the output signal volumes. Register 02h controls the stereo LINE_OUT master volume (both right and left channels), register 04h controls the surround stereo DAC_OUT volume, and register 06h controls the mono volume output. Each step corresponds to 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. ML5 through ML0 is for left channel level, MR5 through MR0 is for the right channel and MM5 through MM0 is for the mono out channel. The default value is 8000h for registers 02h and 06h(8080h for register 38h), which corresponds to 0 dB attenuation with mute on. Table 9. Play Master Volume Register
MUTE 0 0 1
Mx5...Mx0 00 0000 01 1111 xx xxxx
FUNCTION 0dB Attenuation 46.5 Attenuation dB Attenuation
RANGE Req. Req. Req.
4.4.3 PC Beep Register (Index 0Ah)
This register controls the level for the PC Beep input. Each step corresponds to approximately 3 dB of attenuation. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. PC_BEEP supports motherboard implementations. The intention of routing PC_BEEP through the STAC9708/11 mixer is to eliminate the requirement for an onboard speaker by guaranteeing a connection to speakers connected via the output jack. In order for this to be viable the PC_BEEP signal needs to reach the output jack at all times. NOTE: the PC_BEEP is recommended to be routed to L & R Line outputs even when the STAC9708/11 is in a RESET state. This is so that Power On Self Test (POST) codes can be heard by the user in case of a hardware problem with the PC. For further PC_BEEP implementation details please refer to the AC'97 Technical FAQ sheet. The default value can be 0000h or 8000h, which corresponds to 0 dB attenuation with mute off or on.
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Preliminary
Table 10. PC_BEEP Register
STAC9708/11
MUTE 0 0 1
PV3...PV0 0000 1111 xxxx
FUNCTION 0 dB Attenuation 45 dB Attenuation dB Attenuation
4.4.4 Analog Mixer Input Gain Registers (Index 0Ch - 18h, 04h)
These registers control the gain/attenuation for each of the analog inputs. Each step corresponds to approximately 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. Register 0Eh (Mic Volume Register) has an extra bit that is for a 20dB boost. When bit 6 is set to 1, the 20 dB boost is on. The default value is 8008, which corresponds to 0 dB gain with mute on. The default value for the mono registers is 8008h, which corresponds to 0dB gain with mute on. The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on. Table 11. Analog Mixer Input Gain Register
MUTE 0 0 0 1
Gx4...Gx0 00000 01000 11111 xxxxx
FUNCTION +12 dB gain 0 dB gain -34.5 dB gain - dB gain
4.4.5 Record Select Control Register (Index 1Ah)
Used to select the record source independently for right and left. The default value is 0000h, which corresponds to Mic in.
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Preliminary
Table 12, 13. Record Select Control Registers
STAC9708/11
SR2...SR0 0 1 2 3 4 5 6 7
RIGHT RECORD SOURCE Mic CD In (right) Video In (right) Aux In (right) Line In (right) Stereo Mix (right) Mono Mix Phone
SL2...SL0 0 1 2 3 4 5 6 7
LEFT RECORD SOURCE Mic CD In (L) Video In (L) Aux In (L) Line In (L) Stereo Mix (L) Mono Mix Phone
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STAC9708/11
4.4.6 Record Gain Registers (Index 1Ch)
The 1Ch register adjusts the stereo input record gain. Each step corresponds to 1.5 dB. 22.5 dB corresponds to 0F0Fh and 000Fh respectively. The MSB of the register is the mute bit. When this bit is set to 1, the level for that channel(s) is set at - dB. The default value is 8000h, which corresponds to 0 dB gain with mute on. Table 14. Record Gain Registers
MUTE 0 0 1
Gx3... Gx0 1111 0000 xxxx
FUNCTION +22.5 dB gain 0 dB gain - gain
4.4.7 General Purpose Register (Index 20h)
This register is used to control some miscellaneous functions. Below is a summary of each bit and its function. The MS bit controls the mic selector. The LPBK bit enables loopback of the ADC output to the DAC input without involving the AC-Link, allowing for full system performance measurements. Table 15. General Purpose Register
BIT 3D MIX MS LPBK
FUNCTION 3D Stereo Enhancement on/off 1 = on Mono output select 0 = Mix, 1= Mic Mic select 0 = Mic1, 1 = Mic2 ADC/DAC loopback mode
4.4.8 3D Control Register (Index 22h)
This register is used to control the 3D stereo enhancement function, Sigmatel Surround 3D (SS3D), built into the AC'97 component. Note that register bits, DP1-DP0 and DPR1-DPR0 are used to control the separation ratios in the 3D control for both LINE_OUT and DAC_OUT respectively. This allows
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STAC9708/11
for independent control of the stereo enhancement between LINE_OUT and DAC_OUT. SS3D provides for a wider soundstage extending beyond the normal 2-speaker arrangement. Note that the 3D bit in the general purpose register (20h) must be set to 1 to enable SS3D functionality and for the bits in 22h to take effect. Table 16, 17. 3D Control Registers DP1, DP0 LINE_OUT SEPARATION RATIO 0 (Off) 3 (Low) 4.5 (Med) 6 (High) DAC_OUT SEPARATION RATIO 0 (Off) 3 (Low) 4.5 (Med) 6 (High)
00 01 10 11 DPR1, DPR0
00 01 10 11
The three separation ratios are implemented as shown above. The separation ratio defines a series of equations that determine the amount of depth difference (High, Medium, and Low) perceived during two-channel playback. The ratios provide for options to narrow or widen the soundstage.
4.4.9 Multi-Channel Programming Register (Index 74h)
This read/write register is used to program the various options for multi-channel configurations. Only the two LSBs are used (MC0 and MC1), and they define which AC-Link slot data is supplied to the four audio DACs on the STAC9708/11. PCM2 in the table below is the surround stereo DAC, which drives the DAC_OUT pins. The purpose of using slot 10 and 11 in the final configuration is to allow the possibility of an eight channel architecture using two STAC9708 devices in the multi-codec configuration. Also see "Multiple Codec Support" discussion for information on the use of external pins CID1 and CID0.
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Preliminary
Table 18. Multi-Channel Programming Register
STAC9708/11
MC1, MC0
PCM OUT LEFT
PCM OUT RIGHT Slot 4 Slot 8 Slot 9 Slot 9
PCM2 LEFT Slot 7 Slot 6 Slot 7 Slot 10
PCM2 RIGHT Slot 8 Slot 9 Slot 8 Slot 11
0, 0 0, 1 1, 0 1, 1
Slot 3 Slot 7 Slot 6 Slot 6
4.4.10 Powerdown Control/Status Register (Index 26h)
This read/write register is used to program powerdown states and monitor subsystem readiness. The lower half of this register is read only status, a "1" indicating that the subsection is "ready". Ready is defined as the subsection's ability to perform in its nominal state. When this register is written, the bit values that come in on AC-Link will have no effect on read only bits 0-7. Bit 15, When the AC-Link "Codec Ready" indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller must further probe this Powerdown Control/Status Register to determine exactly which subsections, if any are ready. Table 19. Powerdown Status Registers
BIT EAPD REF ANL DAC ADC
FUNCTION External Amplifier Power Down VREF's up to nominal level Analog mixers, etc. ready DAC section ready to playback data ADC section ready to playback data
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STAC9708/11
4.4.10.1 External Amplifier Power Down Control
The EAPD bit 15 of the Powerdown Control/Status Register (Index 26h) directly controls the output of the EAPD output, pin 45, and produces a logical "1" when this bit is set to logic high. This function is used to control an external audio amplifier power down. EAPD = 0 places approximately 0V on the output pin, enabling an external audio amplifier. EAPD = 1 places approximately DVdd on the output pin, disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will likely require an external inverter to maintain software driver compatibility.
4.4.11 Extended Audio ID Register (Index 28)
The Extended Audio ID register is a read only register used to communicate information to the digital controller on two functions. ID1 and ID0 echo the configuration of the codec as defined by the programming of pins 47 and 48 externally. "00" returned defines the codec as the primary codec, while any other code identifies the codec as one of three secondary codec possibilities. SDAC=1 tells the controller that the STAC9708 is a multi-channel codec as defined by the Intel spec.
4.4.12 Extended Audio Status Register (Index 2Ah)
The Extended Audio Status Control register contains two active bits for powerdown and status of the surround DACs. PWD is a read/write bit which is used to powerdown the surround DACs, and SDAC a read only bit to tell the controller when the surround DACs are ready to receive data.
4.4.13 Analog Special Register (Index 6Ch)
The Analog Special Register has two read/write bits used to control two functions specific to the STAC9708. DAC -6dB is used to program the DAC outputs to a -6dB signal level relative to the value of gain already programmed. Similarly, ADC -6dB attenuates any signal input to the ADC by 6dB. This second function is very useful in applications with greater than 1Vrms input levels, as is the case with many CDROMs.
4.4.14 Vendor ID1 and ID2 (Index 7Ch and 7Eh)
These two registers contain four 8-bit ID codes. The first three codes have been assigned by Microsoft using their Plug and Play Vendor ID methodology. The fourth code is a SigmaTel, Inc. assigned code identifying the STAC9708/11. The ID1 register (index 7Ch) contains the value 8384h, which is the first (83h) and second (84h) characters of the Microsoft(R) ID code. The ID2 register (index 7Eh) contains the value 7608h, which is the third (76h) of the Microsoft(R) ID code, and 08h which is the STAC9708/11 ID code.
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STAC9708/11
NOTE: The lower half of the Vendor ID2 register (index 7Eh) currently contains the value 08h identifying the STAC9708/11. This value can be used by the audio driver, or miniport driver in the case of WIN98(R), to adjust software functionality to match the feature-set of the STAC9708/11. This portion of the register will likely contain different values if the software profile of the STAC9708/11 changes, as in the case of silicon level device modifications. This will allow the software driver to identify any required operational differences between the existing STAC9708/11 and any future versions.
5. LOW POWER MODES
The STAC9708/11 is capable of operating at reduced power when no activity is required. The state of power down is controlled by the Powerdown Register (26h). There are 7 commands of separate power down. The power down options are listed in Table 18. The first three bits , PR0..PR2, can be used individually or in combination with each other, and control power distribution to the ADC's, DAC's and Mixer. The last analog power control bit, PR3, affects analog bias and reference voltages, and can only be used in combination with PR1, PR2, and PR3. PR3 essentially removes power from all analog sections of the codec, and is generally only asserted when the codec will not be needed for long periods. PR0 and PR1 control the PCM ADC's and DAC's only. PR2 and PR3 do not need to be "set" before a PR4, but PR0 and PR1 must be "set" before PR4. Table 20. Low Power Modes
GRP BITS PR0 PR1 PR2 PR3 PR4 PR5 PR6 PRJ
FUNCTION PCM in ADC's & Input Mux Powerdown PCM out DACs Powerdown Analog Mixer powerdown (Vref still on) Analog Mixer powerdown (Vref off) Digital Interface (AC-Link) powerdown (extnl clk off) Internal Clk disable Not implemented Powerdown Surround DACs
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Preliminary
STAC9708/11
Figure 12. Example of STAC9708/11 Powerdown/Powerup flow
PR0=1 ADCs off PR0 PR0=0 & ADC=1 PR1=0 & DAC=1 Default PR1=1 PR2=1 PR4=1 Shut off Coda-link
Normal
DACs off PR1
Analog off PR2 or PR3 PR2=0 & ANL=1
Digital I/F off PR4 Warm Reset
Ready =1
Cold Reset
The above figure illustrates one example procedure to do a complete powerdown of STAC9708/11. From normal operation, sequential writes to the Powerdown Register are performed to power down STAC9708/11 a piece at a time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line, issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9708/11 can also be woken up with a cold reset. A cold reset will reset all of the registers to their default states. When a section is powered back on, the Powerdown Control/Status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it.
Figure 13. STAC9708/11 Powerdown/Powerup flow with analog still alive
PR0=1 ADCs off PR0 PR0=0 & ADC=1 PR1=0 & DAC=1 PR1=1 PR4=1 Shut off Coda-link
Normal
DACs off PR1
Digital I/F off PR4 Warm Reset
The above figure illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. This configuration can be used when playing a CD (or external LINE_IN source) through STAC9708/11 to the speakers, while most of the system in low power mode. The procedure for this follows the previous except that the analog mixer is never shut down.
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STAC9708/11
6. MULTIPLE CODEC SUPPORT
The STAC9708/11 provides support for the multi-codec option according to the Intel AC'97, rev 2.1 specification. By definition there can be only one Primary Codec (Codec ID 00) and up to three Secondary Codecs (Codec IDs 01,10, and 11). The Codec ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets; each is individually accessible and they do not share registers.
6.1
Primary/Secondary Codec Selection
In a multi-codec environment the codec ID is provided by external programming of pins 45 and 46 (CID0 and CID1). The CID pin electrical function is logically inverted from the codec ID designation. The corresponding pin state and its associated codec ID are listed in the "Codec ID Selection" table. Also see slot assignment discussion, "Multi-Channel Programming Register (Index 74)". Table 21. Codec ID Selection CID1 STATE +5V or floating +5V or floating 0V 0V CID0 STATE +5V or floating 0V +5V or floating 0V CODEC ID 00 01 10 11 CODEC STATUS Primary Secondary Secondary Secondary
6.1.1 Primary Codec Operation As a Primary device the STAC9708/11 is completely compatible with existing AC'97 definitions and extensions. Primary Codec registers are accessed exactly as defined in the AC'97 Component Specification and AC'97 Extensions. The STAC9708/11 operates as Primary by default, and the external ID pins (47 and 48), have internal pull-ups so that these pins may be left as no-connects for primary operation. When used as the Primary Codec, the STAC9708/11 generates the master AC-Link BIT_CLK for both the AC'97 Digital Controller and any Secondary Codecs. The STAC9708/11 can support up to 4, 10 K 50 pF loads on the BIT_CLK. This is to insure that up to 4 Codec implementations will not load down the clock output. 6.1.2 Secondary Codec Operation When the STAC9708/11 is configured as a Secondary device the BIT_CLK pin is configured as an input at power up. Using the BIT_CLK provided by the Primary Codec insures that everything on the AC-Link will be synchronous. As a Secondary device it can be defined as Codec ID 01, 10, or 11 in the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s).
6.2
Secondary Codec Register Access Definitions
The AC'97 Digital Controller can independently access Primary and Secondary Codec registers by using a 2-bit Codec ID field (chip select) which is defined as the LSBs of Output Slot 0. For Secondary Codec access, the
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Preliminary
STAC9708/11
AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the Codec ID field (Slot 0, bits 1 and 0). As a Secondary Codec, the STAC9708/11 will disregard the Command Address and Command Data (Slot 0, bits 14 and 13) tag bits when it sees a 2-bit Codec ID value (Slot 0, bits 1 and 0) that matches its configuration. In a sense the Secondary Codec ID field functions as an alternative Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator. Secondary Codecs must monitor the Frame Valid bit, and ignore the frame (regardless of the state of the Secondary Codec ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the Secondary Codec ID bits are set. This method is designed to be backward compatible with existing AC'97 controllers and Codecs. There is no change to output Slot 1 or 2 definitions. Table 22. Secondary Codec Register Access Slot 0 Bit Definitions
Output Tag Slot (16-bits) Bit Description 15 Frame Valid 14 Slot 1 Valid Command Address bit (Primary Codec only) 13 Slot 2 Valid Command Data bit (Primary Codec only) 12-3 Slot 3-12 Valid bits as defined by AC'97 2 Reserved (Set to "0") 1-0 2-bit Codec ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary) New definitions for Secondary Codec Register Access
7. TESTABILITY
The STAC9708/11 has two test modes. One is for ATE in-circuit test and the other is restricted for SigmaTel's internal use. STAC9708/11 enters the ATE in circuit test mode if SDATA_OUT is sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs (BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of the AC'97 controller. This case will never occur during standard operating conditions. Once either of the two test modes have been entered, the STAC9704/7 must be issued another rest with all AC-link signals held low to return to the normal operating mode.
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STAC9708/11
8. EXTENDED CODEC FUNCTIONALITY 8.1 Anti-Pop Circuitry
The STAC9708/11 provides an integrated output signal (APOP on pin 34) to aid in low-component-count antipop implementations. An audible speaker "pop" can occur when the main power is applied to, or removed from, the codec or audio output amplifier. In ac coupled systems, the speaker sided of the ac coupling capacitor is shunted to ground through a transistor or FET; this prevents audible pops when the system is powering on and off. A +10 uF capacitor on CAP1 provides a delay to hold-off power to the output stages on power up. A +22 uF capacitor provides reserve power to sustain the output shunting action until the power has been fully removed on power down. APOP is active logic high during shunting operations; APOP is at logic low during normal operations.
9. AC TIMING CHARACTERISTICS
(Tambient = 25 C, AVdd = DVdd = 5.0V or 3.3V 5%, AVss=DVss+0V; 50pF external load)
9.1 Cold Reset
Figure 14. Cold Reset
Trst2clk Tres_low
RESET# BIT_CLK
Table 23. Cold Reset PARAMETER RESET# active low pulse width RESET# inactive to BIT_CLK startup delay # denotes active low. SYMBOL Tres_low Trst2clk MIN 1.0 162.8 TYP MAX UNITS us ns
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9.2 Warm Reset
Preliminary
STAC9708/11
Figure 15. Warm Reset
Tsync_high Tsync_2clk
SYNC BIT_CLK
Table 24. Warm Reset PARAMETER SYNC active high pulse width SYNC inactive to BIT_CLK startup delay SYMBOL Tsync_high Tsync2clk MIN 162.8 TYP 1.3 MAX UNITS us ns
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9.3 Clocks
Preliminary
STAC9708/11
Figure 16. Clocks
Tclk_low
BIT_CLK
Tclk_high
Tclk_period Tsync_low
SYNC
Tsync_high
Tsync_period
Table 25. Clocks PARAMETER BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BLT_CLK high pulsewidth (note 1) BIT_CLK low pulse width (note 1) SYNC frequency SYNC period SYNC high pulse width SYNC low_pulse width SYMBOL Tclk_period Tclk_high Tclk_low Tsync_period Tsync_high Tsync_low MIN 32.56 32.56 TYP 12.288 81.4 40.7 40.7 48.0 20.8 1.3 19.5 MAX 750 48.84 48.84 UNITS MHz ns ps ns ns kHz us us us
Notes: 1) Worst case duty cycle restricted to 40/60.
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9.4 Data Setup and Hold
Preliminary
(50pF external load) Figure 17. Data Setup and Hold
STAC9708/11
Tsetup
BIT_CLK SDATA_IN SDATA_OUT
Thold
SYNC
Tsetup Thold
Table 26. Data Setup and Hold
PARAMETER Setup to falling edge of BIT_CLK Hold from falling edge of BIT_CLK
SYMBOL Tsetup Thold
MIN 15.0 5.0
TYP -
MAX -
UNITS ns ns
Note 1: Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller.
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9.5 Signal Rise and Fall Times - (50pF external load; from 10% to 90% of Vdd)
Figure 18. Signal Rise and Fall Times BIT_CLK
Triseclk Tfallclk
SDATA_IN
Trisedin Tfalldin
Table 27. Signal Rise and Fall Times
PARAMETER BIT_CLK rise time BIT_CLK fall time SDATA_IN rise time SDATA_IN fall time
SYMBOL Triseclk Tfallclk Trisedin Tfalldin
MIN 2 2 2 2
TYP -
MAX 6 6 6 6
UNITS ns ns ns ns
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9.6 AC-Link Low Power Mode Timing
Figure 19. AC-Link Low Power Mode Timing
SYNC BIT_CLK
Slot 1
Slot 2
SDATA_OUT SDATA_IN
Write to 0x20
Data PR4
Don't care
Ts2_pdown
Note: BIT_CLK not to scale
Table 28. AC-Link Low Power Mode Timing
PARAMETER End of Slot 2 to BIT_CLK, SDATA_IN low
SYMBOL Ts2_pdown
MIN -
TYP -
MAX 1.0
UNITS us
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9.7 ATE Test Mode
Preliminary
STAC9708/11
Figure 20. ATE Test Mode
RESET# SDATA_OUT
Tsetup2rst Hi-Z
SDATA_IN, BIT_CLK
Toff
Table 29. ATE Test Mode PARAMETER Setup to trailing edge of RESET# (also applies to SYNC) Rising edge of RESET# to Hi-Z delay Notes: SYMBOL Tsetup2rst Toff MIN 15.0 TYP MAX 25.0 UNITS ns ns
1. 2.
All AC-Link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the trailing edge of RESET# causes STAC9708/11's AC-Link outputs to go high impedance which is suitable for ATE in circuit testing. Once either of the two test modes have been entered, the STAC9708/11 must be issued another RESET# with all AC-Link signals low to return to the normal operating mode.
# denotes active low.
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10. ELECTRICAL SPECIFICATIONS: 10.1 Absolute Maximum Ratings:
Voltage on any pin relative to Ground Operating Temperature Storage Temperature Soldering Temperature Output Current per Pin Vss - 0.3V TO Vdd + 0.3V 0 oC TO 70 o C -55 oC TO +125 o C oC FOR 10 SECONDS 260
4 mA except Vrefout = 5mA
10.2 Recommended Operating Conditions
Table 30. Operating Conditions PARAMETER Power Supplies + 3.3V Digital + 5V Digital + 5V Analog + 3.3V Analog MIN 3.135 4.75 4.75 3.135 0 TYP 3.3 5 5 3.3 MAX UNITS 3.435 5.25 5.25 3.435 70 V V V V oC
Ambient Temperature
SigmaTel reserves the right to change specifications without notice.
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10.3 Power Consumption
Preliminary
Table 31. Power Consumption PARAMETER MIN + 5V Digital + 3.3V Digital + 5V Analog + 3.3V Analog TYP 55 35 80 70 68 54 40 30 0.1 0.1 0.1
STAC9708/11
MAX
UNITS mA mA mA mA mA mA mA mA mA mA mA
Digital Supply Current Analog Supply Current Power Down Status PR0 +5V Analog Supply Current PR1 +5V Analog Supply Current PRJ +5V Analog Supply Current PR2 +5V Analog Supply Current PR3 +5V Analog Supply Current PR4 +3.3V Digital Supply Current PR4 +5V Digital Supply Current PR5 No effect
10.4 AC-Link Static Digital Specifications
AVss=DVss=0V; 50pF external load)
(Tambient = 25 oC, DVdd = 5.0V or 3.3V 5%,
Table 32. AC-Link Static Specifications PARAMETER Input Voltage Range Low level input range High level input voltage High level output voltage Low level output voltage Input Leakage Current (AC-Link inputs) Output Leakage Current (Hi-Z'd AC-Link outputs) Output buffer drive current SYMBOL Vin Vil Vih Voh Vol MIN -0.30 0.40xDVdd 0.50xDVdd -10 -10 4 TYP MAX DVdd + 0.30 0.30xDVdd 0.2xDVdd 10 10 UNITS V V V V V uA uA mA
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10.5 STAC9708 Analog Performance Characteristics (Tambient = 25 oC, AVdd = 5.0V 5%,
DVdd = 3.3V 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0 dB = 1 Vrms, 10K/50pF load, Testbench Characterization BW: 20 Hz - 20 kHz, 0 dB settings on all gain stages) Table 33. Analog Performance Characteristics
PARAMETER Full Scale Input Voltage: Line Inputs Mic Inputs1 Full Scale Output Voltage: Line Output 5V Analog S/N: CD to LINE_OUT 5V Other to LINE_OUT 5V Analog Frequency Response2 Digital S/N D/A 5V A/D 5V Total Harmonic Distortion: Line Output4 D/A & A/D Frequency Response5 Transition Band Stop Band Stop Band Rejection Group Delay Power Supply Rejection Ratio (1kHz) Crosstalk between Input channels Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance Input Capacitance Vrefout
6 7 3
MIN 90 20 85 75 20 19,200 28,800 +85 10 47
TYP 1.0 0.1 1.0 98 98 96 86 +40 +40 +100 1.5 15 0.41 x AVdd
MAX 20,000 0.02 19,200 28,800 - - 1 - -70 - - - - -
UNITS Vrms
Vrms dB Hz dB
% Hz Hz Hz dB dB ms dB dB dB dB K pF V
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Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset Voltage Deviation from Linear Phase External Load Impedance Mute Attenuation (Vrms input)
Preliminary
0.5 100 10 10 90 96 50 1 0.5
STAC9708/11
dB dB ppm/deg. C mV degree K ohm dB
Notes: 1. With +20 dB Boost on, 1.0Vrms with Boost off 2. 1 dB limits 3. The ratio of the rms output level with 1 kHz full scale input to the rms output level with all zeros into the digital input. Measured "A weighted" over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 4. 0 dB gain, 20 kHz BW, 48 kHz Sample Frequency 5. 0.25dB limits 6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output.
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(Tambient = 25 oC, AVdd = DVdd = 3.3V 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0 dB = 1 Vrms, 10K/50pF load, Testbench Characterization BW: 20 Hz - 20 kHz, 0 dB settings on all gain stages)
10.6 STAC9711 Analog Performance Characteristics
Table 34. Analog Performance Characteristics
PARAMETER Full Scale Output Voltage: Line Inputs to line output 3.3V Line Inputs to LINE_OUT 3.3V @ Line In = 1 Vrms and @ Gain setting of -6 dB Line Inputs to LINE_OUT 3.3V @ Line In = 0.5 Vrms and @ gain setting of 0dB PCM to LINE_OUT 3.3V @ full scale PCM input @PCM gain setting of 0dB PCM to Line Output 3.3V MIC Inputs to LINE_OUT 3.3V @ MIC In = 1 Vrms and @ gain setting of 0dB Analog S/N: CD to LINE_OUT 3.3V Other to LINE_OUT 3.3V Analog Frequency Response2 Digital S/N D/A 3.3V A/D 3.3V Total Harmonic Distortion: Line Output4 D/A & A/D Frequency Response5 Transition Band Stop Band Stop Band Rejection Group Delay Power Supply Rejection Ratio (1kHz) Crosstalk between Input channels
6 7 3
MIN -
TYP 0.5 0.5 0.5 0.5 0.5
MAX -
UNITS Vrms Vrms Vrms Vrms Vrms
20 85 75 20 19,200 28,800 +85 -
90 90 90 85 +40 +40 -
20,000 0.02 19,200 28,800 - - 1 - -70 % Hz Hz Hz dB dB ms dB dB Hz
Out-of-Band Rejection
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Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance Input Capacitance Vrefout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset Voltage Deviation from Linear Phase External Load Impedance Mute Attenuation (0 dB)
Preliminary
10 +100 1.5 15 0.41 x AVdd 100 10 10 90 96
STAC9708/11
- - - - - 0.5 0.5 50 1 dB dB K pF V dB dB ppm/ oC mV degree K dB
Notes: 1. With +20 dB Boost on, 1.0Vrms with Boost off 2. 1 dB limits 3. The ratio of the rms output level with 1 kHz full scale input to the rms output level with all zeros into the digital input. Measured "A weighted" over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 4. 0 dB gain, 20 kHz BW, 48 kHz Sample Frequency 5. 0.25dB limits 6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output.
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Appendix A
SPLIT INDEPENDENT POWER SUPPLY OPERATION
STAC9708/11
In PC applications, one power supply input to the STAC9708/11 may be derived from a supply regulator (as shown in Figure 3) and the other directly from the PCI power supply bus. When power is applied to the PC, the regulated supply input to the IC will be applied some time delay after the PCI power supply. Without proper onchip partitioning of the analog and digital circuitry, some manufacturer's codecs would be subject to on-chip SCR type latch-up. SigmaTel's STAC9708/11 specifically allows power-up sequencing delays between the analog (AVddx) and digital (VDddx) supply pins. These two power supplies can power-up independently and at different rates with no adverse effects to the codec. The IC is designed with independent analog and digital circuitry that prevents on-chip SCR type latch-up.
3.3V or 5V 5% * AVdd must always be >= DVdd 3.3V or 5V 5% 0.1uF 0.1uF 1uF 0.1uF
REG 10uF
0.1uF
25 AVdd1 12 P C _B E E P 13 PHONE 14 AUX_L
38 AVdd2
1 DVdd1
9 DVdd2 XTL_IN 24.576MHz XTL_OUT 3 5 6 BIT_CLK 8 2 33pF
33pF
SDATA_OUT
15 AUX_R 16 VIDEO_L
SDATA_IN
S igm a T e l
10 SYNC 11 RESET 45 CID0 46 CID1
17
VIDEO_R 18 CD_L
S T A C 9 7 0 8 /11
19
CD_GND 20 CD_R 21 MIC1 22 MIC2 23 CAP1 Vrefout 32 CAP2 31 33 27 Vref 0.1uF 28 10uF
10uF
0.1uF
LINE_IN_L
CAP3 24
10uF 22uF
LINE_IN_R
45 APOP 34 47 EAPD 46 35 LINE_OUT_L 36
CID0
CID1
560 - 1000pF 29 560 - 1000pF 30 AFILT2 AFILT1
LINE_OUT_R
37 MONO_OUT
AVss1
26
AVss2 42
DVss1 4
DVss2 7
DAC_OUT_L 39
DAC_OUT_R 41
** Teminate ground plane as close to power supply as possible
NOTE: Pins 31, 33, 34, 40
43, 44, and 48 are No Connects Brd Analog Gnd Brd Digital Gnd
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Appendix B
+5.0V/+3.3V POWER SUPPLY OPERATION NOTES
STAC9708/11
The STAC9708 is capable of operating from a single 5V supply connected to both DVdd and AVdd. Even though the STAC9708 has digital switching levels of 0.2Vdd to 0.5Vdd (See AC Link Electrical Characteristics in this data book), we recommend that all digital interface signals to the AC-Link be 5V. If digital interface signals below 5V are used, then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity. The STAC9708 can also operate from a 3.3V digital supply connected to DVdd while maintaining a 5V analog supply on AVdd. On-chip level shifters ensure accurate logic transfers between the analog and digital portions of the STAC9708. If digital interface signals above 3.3V are used (i.e. a +5V AC-Link interface), then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity and to prevent on-chip ESD protection diodes from turning on. (See Appendixes A concerning SPLIT INDEPENDENT POWER SUPPLY OPERATION). The STAC9711 must be run from a 3.3V supply connected to both DVdd and AVdd. If digital interface signals above 3.3V are used (i.e. a +5V AC-Link interface), then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity and to prevent on-ship ESD protection diodes from turning on. *Always operate the STAC97xx digital supply from the same supply voltage as the digital controller supply. *All the analog inputs must be ac-coupled with a capacitor of 3.3 uF or greater. It is recommended that a resistor of about 47K be connected from the signal side of the capacitor to analog GND as shown below.
> 3.3 uF SIGNAL 47K Analog Input
*All the analog outputs must be ac-coupled. If an external amplifier is used, make sure that the input impedance of the amplifier is at least 10K and use an ac-coupling capacitor of 3.3 uF.
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Preliminary - NOTES -
STAC9708/11
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STAC9708/11
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Preliminary
For more information, please contact:
STAC9708/11
SigmaTel, Inc.
6101 W. Courtyard Dr., Bldg. 1, Suite 100 Austin, Texas 78730 Tel (512) 343-6636, Fax (512) 343-6199 email: sales@sigmatel.com Homepage: www.sigmatel.com
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